Model & Context Deck
Hardware Compatibility & Generation Speed
Estimated autoregressive decode speed (tokens/sec) based on physical memory bandwidth.
Calculate exact memory footprints for model weights, Grouped-Query Attention (GQA) KV caches, and activation buffers across quantization levels. Project memory-bandwidth bound generation speeds (tokens/sec) and verify physical hardware compatibility before deploying.
Estimated autoregressive decode speed (tokens/sec) based on physical memory bandwidth.
Why does a model take twice as much VRAM at 64k context? Why does token generation speed depend entirely on memory bandwidth rather than GPU compute TFLOPS? Understand the underlying physics of machine learning hardware.
During LLM generation (the decode phase), the model predicts one token at a time. To emit a single token, every single parameter weight must be read from VRAM into the GPU's register files and tensor cores.
For example, an RTX 4090 has 1,008 GB/s memory bandwidth. A 70B model at Q4_K_M is roughly 40 GB. To generate 1 token, the GPU must stream 40 GB across the bus. At 1,008 GB/s, the theoretical upper bound is:
No matter how many TFLOPS of compute you have, generation speed is physically locked to the speed of your memory bus.
In standard Multi-Head Attention (MHA), every query head has its own dedicated Key and Value heads ($n_{kv} = n_{heads}$). At 128k context, standard MHA causes the KV cache to balloon past 100 GB.
Modern models like Llama 3.3 and Qwen 2.5 use Grouped-Query Attention (GQA), where multiple query heads share a single key/value head (e.g. 8 KV heads for 64 query heads = 8:1 ratio).
This reduces the KV cache footprint by an astonishing 87.5% (8× smaller), allowing long-context documents to fit on consumer GPUs.
Standard model training operates in 16-bit floating point (FP16/BF16), requiring 2.0 bytes per parameter. Quantization compresses weights into lower bit representations:
Modern k-quants use block-level scales and offsets so that sensitive layers (attention matrices) retain higher bit precision while feedforward layers are compressed.
Study Hardware 600: The Silicon & Hardware Behind AI for tensor core scheduling, systolic arrays, and HBM memory controllers.